SDR-IP
Software Defined Radio Over IP
FUTURE PRODUCT
The high performance SDR-IP is an ethernet protocol (IP) software defined radio. The SDR-IP utilizes a high speed FPGA and a 16 bit direct sampling ADC with fully upgradable plug-in interface board and firmware.
The SDR-IP uses a high performance 80 MHz, 16 bit ADC with both dithering and randomization for best performance. The output I/Q bandwidth is fully configurable via software. PC communications are handled over a 100 base-T port using 24 bit I/Q words. A TCP connection is used to control the radio and a UDP connection is used to transfer the data back to the PC. The ethernet port allows easy interfacing to Mac OSX, Windows, and Linux without the need of additional drivers. The communications protocol will be fully documented. The use of IP protocol, allows the radio to be operated over the intranet. The SDR-IP ships with the latest version of SpectraVue software for Windows.
PRELIMINARY
Frequency Range: 0.01 - 32 MHz *
Digital Down Converter: Xilinx XC3S500E
PC Interface: Ethernet 100 base-T
Filters: 32 bit ,120+ dB 94% Alias Free BW
Output Flatness: 0.1 dB
Dynamic Range: 104 dB
MDS: -132dBm in 500 Hz BW
Analog to Digital Converter: 16bit
Preselection: 10 Filters
Attenuators: 0, -10dB, -20dB, -30dB
Sample Rate: 80 MHz
Memory: 65536 x 16 bit samples
External Radio Control: Built-in RS-232 port
Dimensions: 210 x 70 x 180 mm
Display: 16 x 2 Character LED LCD
Power: 5 Volts DC @ 1.5 Amp **
Connections: 2 x BNC (HF/Optional downconverter), DB-9 (serial out), Ethernet, Power
Expansion: Internal Downconverter, Internal High Speed FPGA Bus.
Introducing the SDR-IP digital radio
Future Options
6MTR: Adds 50-54 MHz band.
2MTR: Adds 144-148 MHz band.
FMDC: Adds 88-108 MHz band.
1GDUC: Adds Digital Up Converter. SMA Out.
LNLCK: Adds Low Noise VC-OCXO (+/- 1ppm) plus 10 MHz Phase Lock.
* Optional internal downconverter with separate antenna inputs.
** Options may require additional current
PRELIMINARY SPECS MAY CHANGE WITHOUT NOTICE.
The digital down converter used in the SDR-IP if fully configurable. It uses a Xilinx XC3S500E FPGA. The digital filters offer over 120dB of image rejection in a 94% of Fs bandwidth. This gives a very efficient 470 KHz usable BW for a 500 KHz output sample rate. The high performance receive modes use 32 bit precision and are rounded to 24 bits before being sent to the PC.
The analog front end uses a high dynamic range preamp with a bank of 10 preselector filters and 2 switchable attenuators. RF switching uses relays for better IMD. The HF antenna port also includes a gas discharge tube for high voltage transients.
The SDR-IP can be configured with a low phase noise 80 MHz encode clock. This oscillator can be locked to reference clocks like GPS and rubidium standards. When not externally locked, the oscillator has a stability of +/- 1 ppm over temperature. The phase noise at 10 KHz is -170 dBc/Hz typical.
The SDR-IP is built for upgradeability. Future PC interfaces or more powerful FPGAs can be accommodated by just replacing the digital board. There is also room inside for three additional full size boards and a plug-in frequency downconverter with its own RF input connector. In addition, its high speed expansion port will be used for some really exciting applications.
The SDR-IP is housed in a solid aluminum, shielded extruded enclosure.
(c) 2008 RFSPACE, Inc..